Digital SoC Design Verification Principal Engineer/Manager

We are looking for an experienced Digital SoC Design Verification Principal Engineer/Manager to lead a team of engineers in developing innovative Open RAN SoC functional blocks for 5G cellular base stations. In this role, you will be responsible for driving the development of high-quality digital solutions and contributing to product definition. You will ensure successful product implementation through effective verification strategies.

As a key leader, you will oversee the creation of comprehensive verification plans, evaluate verification coverage, and ensure seamless integration of in-house and third-party IP. You will also collaborate across the organization, working closely with Product Management, System Engineering, and HW/FW Design teams to align high-level requirements with implementation. Your leadership will be crucial in driving the success of complex SoC projects from initial concept to mass production.

This full-time position is in San Jose, CA.

Key Responsibilities:

• Verification Planning and Execution:
• Create, manage, and drive comprehensive product verification plans for complex SoCs, ensuring all functional requirements are thoroughly validated.
• Continuously evaluate verification coverage, identify gaps, and implement mitigation strategies to ensure thorough testing.
• Oversee the SoC verification process from start to finish, ensuring timely and high-quality results.
• Cross-functional Collaboration:
• Collaborate with Systems Engineering and HW/FW Design teams to ensure clear understanding of product requirements and implementation strategies.
• Contribute to and review SoC specifications and architectures from a verification perspective to ensure feasibility and completeness.
• Team Leadership and Development:
• Lead, mentor, and grow a team of engineers, providing strategic direction and fostering a culture of innovation and excellence.
• Manage hiring, resource planning, performance management, and the scheduling of verification efforts across multiple projects.
• Create a collaborative environment to ensure team members’ growth through knowledge sharing, coaching, and continuous learning.
• Product Delivery and Debugging:
• Support the debugging of verification failures and facilitate resolution through detailed analysis and proactive mitigation.
• Own the process of bringing highly integrated mixed-signal SoCs from concept to mass production, ensuring all verification and product requirements are met.
• Continuous Improvement:
• Drive the development and adoption of best practices in SoC verification, leveraging new tools and technologies such as UVM, formal verification, and continuous integration techniques.
• Maintain a deep understanding of digital SoC intricacies, including high-performance design, multiple clock domains, and wireless communication protocols.

Job Requirements:

• Master's and/or Bachelor’s degree in engineering (or equivalent) in EC/ EE/ CS
• At least 15 years of experience in digital SoC verification, with 5 years in a leadership or management role.
• Proven success in leading complex SoC verification projects from concept to mass production, demonstrating strong leadership and technical expertise.
• Hands-on experience in SystemVerilog, Verilog, mixed-signal SoC simulation, and FPGA-based verification.
• Deep understanding of digital and mixed-signal IP integration, including custom RTL and digital/analog co-verification.
• Familiarity with HW emulators, embedded systems, wireless protocols, and signal processing.
• Proficiency in programming languages such as C, Python, and Tcl for test bench architectures and automation.
• Demonstrated ability to lead, manage, and mentor a dispersed engineering team, fostering a high-performance culture.
• Strong schedule and resource management background, with an ability to prioritize tasks effectively across multiple projects.
• Excellent communication and presentation skills, capable of effectively conveying technical details to both technical and non-technical stakeholders.

 Desirable Skills:

• Track record of successfully executing block or chip-level verification plans.
• Deep understanding of the complete verification life cycle (test plan, testbench through coverage closure).
• Knowledge of Cadence verification tools and UVM verification methodologies.
• Experience with wireless communication standards such as 3GPP, WiFi, 4G/5G, or similar technologies.
• Ability to thrive in environments with changing or incomplete requirements while developing creative solutions and workarounds.

Compensation and Benefits:

At InnoPhase, our compensation package includes base pay and pre-IPO stock options. The base pay range for this role is between $140K-$225K. Your base pay will depend on the market, interview results, skills, qualifications, experience, education, and location. Our employee benefits include a comprehensive group health plan, matching 401(k), training reimbursement, and various paid leaves (vacation, sick, holidays, maternity/paternity leave, jury). Visit our website to learn more about our employee benefits.