Principal Static Timing Analysis (Sta) Engineer - Soc Design
Automate your job search with Sonara.
Submit 10x as many applications with less effort than one manual application.1
Reclaim your time by letting our AI handle the grunt work of job searching.
We continuously scan millions of openings to find your top matches.
Job Description
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
The DCE team at Marvell is seeking a Principal Static Timing Analysis (STA) Engineer to contribute to a wide range of innovative projects-from artificial intelligence and machine learning to advanced wired and wireless infrastructure-using the latest technology nodes.
Our team leverages cutting-edge EDA tools to solve complex challenges and ensure our designs meet critical performance, power, and area (PPA) goals. This role involves close collaboration with Physical Design, Design for Test (DFT), and other cross-functional teams across both local and global sites.
If you're looking to apply your STA expertise in a dynamic and forward-thinking environment, this could be a great opportunity to explore.
What You Can Expect
Lead timing closure for sub-system/partition or full-chip level designs.
Collaborate with RTL, DFT, and IP teams to drive iterative timing feedback and closure.
Deliver timing collateral and signoff reports per project milestones.
Perform timing correlation between PD tools and signoff tools; support early feasibility studies.
Generate and push down ECOs to block-level teams.
Mentor junior engineers and provide technical leadership across teams.
Develop automation scripts in Perl, Python, and TCL to improve timing workflows.
Manage timing constraints compatible with synthesis, P&R, and STA tools.
What We're Looking For
BS in EE/CE/CS with 10+ years (or MS with 5+ years) of relevant experience.
Proven success in timing analysis and closure across multiple ASICs/SoCs.
Experience with advanced timing concepts: SI, CDC, LVF, POCV, etc.
Proficiency in STA tools (e.g., Synopsys PrimeTime), scripting, and UNIX environments.
Strong communication skills and ability to work independently and collaboratively.
Preferred Qualifications
15+ years of experience (BS) or 10+ years (MS) in STA and timing closure.
Experience leading timing closure efforts across teams.
Familiarity with timing methodology and flow development.
Expected Base Pay Range (USD)
148,500 - 219,780, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
#LI-TM1