Physical Design for Machine Learning Intern

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

As an intern in the Physical Design (PD) team, you will work on high-performance designs going into industry leading AI/ML architectures. The student coming into this role will develop ML-based tools and flows to improve the PPA (Performance Power Area) and turnaround time for all aspects of chip implementation from synthesis to tapeout for various IPs. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is on-site, 40 hours, based out of Santa Clara, CA or Austin, TX.

Who You Are

• Currently pursuing a BS, MS, or PhD in EE, ECE, CE, CS, or a related field.
• Comfortable programming in Python and C/C++, with a strong grasp of data structures and algorithms.
• Passionate about applying machine learning to real-world engineering problems.
• Familiar with the basics of VLSI design or curious to learn more about the chip design process.

What We Need

• Collaborate with physical design engineers to build ML-based tools for areas like synthesis, place-and-route, and timing closure.
• Extend existing ML systems and experiment with new algorithms to improve chip implementation flows.
• Select, represent, and manage datasets drawn from real chip design workflows.
• Run ML experiments, analyze performance, and fine-tune models to improve turnaround time and PPA.

What You Will Learn

• How ML is being used to drive the next generation of chip design tools.
• The fundamentals of physical design and ASIC implementation from synthesis through tapeout.
• How to apply statistical and algorithmic thinking to real silicon design data.
• What it’s like to work closely with experienced engineers solving high-impact, industry-level problems.