Principal CPU Design Verification Engineer

Ventana is building the highest-performance RISC-V CPUs on the planet-designed for data center, AI, and edge workloads, with real silicon, not slideware.

Our second-generation Veyron core (V2) is on track to ship early next year, featuring an aggressive wide-issue pipeline and built in 4nm. Development on Veyron V3 is ramping now, with even greater performance and deep AI platform integration. This is your opportunity to work alongside engineers who built iconic processors like the AMD K6 and the first 64-bit ARM server processor (X-Gene at AppliedMicro)-bringing decades of CPU innovation to a clean-slate, open-standards future. You can check us out here: Ventana Micro - YouTube

Principal CPU Design Verification Engineer:

We are seeking an experienced verification engineer to lead verification efforts of complex CPU and related subsystems based on the open-source RISC-V architecture. The right candidate will have deep technical expertise combined with exceptional leadership skills.

Responsibilities:

• Lead end-to-end verification from complex CPU sub-units up to CPU clusters, partnering with architecture and design teams

• Develop verification infrastructure components including test-benches, scoreboards, and stimulus generators

• Develop and execute comprehensive verification plans for units and features

• Implement functional coverage models

• Debug designs in simulation, prototyping platforms, and silicon

• Continuously drive methodology improvements to improve efficiency

• Lead senior and junior engineers as a team to accomplish successful projects

Minimum Qualifications:

• Bachelors or Masters degree in electrical, computer engineering or related field

• BS+10 years or MS+12 years of industry experience successfully delivering CPU implementations

Skills & Qualifications Required:

• SystemVerilog verification development experience

• Testbench construction using UVM or analogous methodologies

• Scoreboards and stimulus generators for complex units

• Strong background in one or more common CPU ISAs. x86, ARM, MIPS, RISC-V, etc.

• Strong background in processor coherency and MP programming

• Project ownership throughout the project lifecycle

• Demonstrated team leadership experience with outstanding communication skills

• Highly motivated self-starter with strong execution mindset and collaborative approach

• Post-silicon debug experience strongly preferred

BASE SALARY RANGE

$105,000 TO $260,000 per year

EEOE

Ventana is an Equal Employment Opportunity Employer. We value diversity and uphold an inclusive environment where all people feel that they are equally respected and valued. Qualified applicants will receive consideration without regard to race, color, creed, religion, sex, sexual orientation, national origin or nationality, ancestry, age, disability, gender identity or expression, marital status, veteran status, or any other category protected by law.

COVID-19

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