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Asic Design-For-Test (Dft)

Accord Technologies Inc.San Jose, CA

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Job Description

Role: Lead ASIC DFT Engineer• Location: San Jose, CA• Work Setup: Remote, PST time zone• Nbr of openings: 4 positions. • Visa type: Any Visa who can work in PST time zone • Position type: W2 or C2C

Mandatory skills:• DFT Architecture definition. Must• Full chip / Sub system level DFT activities Must• Scan & compression (EDT) implementation • LBIST implementation and verification any BIST exp • Coverage improvements (Spyglass work) • ATPG

Experience Required:

  • 10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

Key Skills Required:

  • Strong hands-on ASIC DFT experience with end-to-end ownership
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug
  • Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools
  • Strong background in scan insertion, scan chain stitching, ATPG setup, simulation, debug, and DRC analysis
  • MBIST implementation and verification; SMS experience preferred
  • Tessent/SSN experience preferred
  • Strong understanding of PLLs, RTL design, synthesis, LEC, and physical design flows
  • Post-silicon debug and silicon bring-up experience TCL, PERL, or Python scripting experience is highly preferred

I need skill metrics on:

  1. DFT Architecture
  2. Scan & compression(EDT) implementation
  3. LBIST implementation and verification
  4. Coverage improvements (Spyglass work)
  5. ATPG sims - timing & no timing.
  6. Full chip / Sub system level DFT activities.

Please prioritize this requirement and send relevant profiles at the earliest possible opportunity.

Thank you, and I look forward to your quick support.

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FAQs About Asic Design-For-Test (Dft) Jobs at Accord Technologies Inc.

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This job at Accord Technologies Inc. is located in San Jose, CA, according to the details provided by the employer. Some roles may also include multiple work locations depending on the requirement.
What pay range can candidates expect for this role at Accord Technologies Inc.?
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