ASIC Design Manager

ASIC Design ManagerThis role has been designed as ‘Hybrid’ with an expectation that you will work on average 2 days per week from an HPE office.

Job Description:

Overview

Role focuses on advanced silicon, block and system level ASIC/SoC design and development. Responsibilities include designing, developing, analyzing, troubleshooting, and debugging complex ASIC and SoC architectures, RTL implementations, and integration flows. Supports development of products, services, and solutions within HPE’s networking portfolio. Requires strong expertise in hardware design engineering disciplines, methodologies, and tools—including SystemVerilog RTL development, microarchitecture design, integration, synthesis, and silicon implementation flows.

Leads and mentors a team of ASIC design engineers responsible for developing RTL, driving microarchitecture implementation, and ensuring high quality silicon design and integration. Partners closely with architects, verification leads, and cross functional teams to align design execution with product architecture and program goals.

Management Level Definition:

Applies advanced subject matter knowledge to manage staff activities in solving common and complex business/technical issues within established policies. Manages exempt individual contributors and/or supervisors. Has accountability for results of a major program in terms of cost, direction and people management. Provides guidance on process improvements and recommends changes in alignment with business tactics and strategy for area of responsibility. Plans, manages and monitors operational/tactical activities of Staff. Staff members' work may involve strategic issues. Recruits and supports development of direct staff members. Typically reports to MG2 or Director.

Responsibilities

Leads a team of ASIC design engineers focused on block and subsystem implementation using SystemVerilog RTL and modern ASIC design flows

Drives development and implementation of microarchitecture and RTL designs aligned with product architecture and performance goals

Creates design plans, schedules, milestones, and priorities based on product architecture and program needs

Ensures high quality RTL implementation, including functional correctness, performance, power efficiency, and design robustness

Oversees block integration and subsystem development, ensuring alignment across design, verification, and system architecture

Works closely with verification teams to support verification planning, debug, and coverage closure

Manages team execution, schedules, deliverables, and continuous improvement in design methodologies, automation, and productivity

Collaborates with architects, verification leads, program management, validation, and system engineering to communicate status and drive issue resolution

Works with EDA vendors and global development partners to support design tools, synthesis flows, and silicon development infrastructure

Identifies opportunities for design methodology improvements, flow innovation, and productivity enhancements

Provides people leadership including hiring, mentoring, performance planning, and skill development

Education and Experience Required

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent; advanced degree preferred

Typically 7–10 years of ASIC/SoC design and development experience

2–5+ years of people management or technical leadership in ASIC design or silicon development

Strong hands on expertise in SystemVerilog RTL development, microarchitecture design, and ASIC implementation flows

Experience with ASIC integration, synthesis, timing closure, and design debugging

Networking experience is desirable

Knowledge and Skills

Strong leadership and team building skills with ability to guide senior technical contributors

Deep knowledge of ASIC/SoC design methodologies, microarchitecture development, RTL coding practices, and integration flows

Solid understanding of silicon development flows from architecture definition through tape out and post silicon bring up

Experience collaborating closely with verification, physical design, and system teams

Strong organizational and planning skills with ability to manage schedules and priorities

Ability to work effectively with geographically distributed teams and external partners

Excellent communication skills for technical and cross functional audiences

Strong problem solving skills and ability to influence design strategy and execution

Additional Skills:

Accountability, Accountability, Action Planning, Active Learning, Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross-Functional Teamwork, Data Analysis Management, Data Collection Management (Inactive), Data Controls, Design, Design Thinking, Empathy, Follow-Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity (Inactive), Long Term Planning, Managing Ambiguity {+ 5 more}

What We Can Offer You:

Health & Wellbeing

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.

Personal & Professional Development

We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.

Unconditional Inclusion

We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

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Job:

Engineering

Job Level:

Manager_1

"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level. – United States of America: Annual Salary USD 153,500 - 310,500 in CaliforniaThe listed salary range reflects base salary. Variable incentives may also be offered."

Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html

Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.

HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.

No Fees Notice & Recruitment Fraud Disclaimer

It has come to HPE’s attention that there has been an increase in recruitment fraud whereby scammer impersonate HPE or HPE-authorized recruiting agencies and offer fake employment opportunities to candidates.  These scammers often seek to obtain personal information or money from candidates.

Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.  The credentials of any hiring agency that claims to be working with HPE for recruitment of talent should be verified by candidates and candidates shall be solely responsible to conduct such verification. Any candidate/individual who relies on the erroneous representations made by fraudulent employment agencies does so at their own risk, and HPE disclaims liability for any damages or claims that may result from any such communication.