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Core Engineering - Design Engineer V

Artech LLCSunnyvale, CA
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Job Description

Title: Design Engineer VDuration: 6+ months (possible extension)Location: Sunnyvale, CA (HYBRID)

DUTIES: ASIC Power Engineer to perform power analysis and optimizations in ASIC for Meta’s AR/VR products. Areas of interests includes Machine Learning. Primary languages are Python, tcl and SystemVerilog.

What makes this role interesting? Value added or experience gained?:

Designing the most advanced chips for AR/VR devices, META owns the major market for VR devices, there is a lot of opportunities to learn on how to build chips for AR/VR products, you will learn on how to build a chip and how to collaborate with software and hardware folks.

RESPONSIBILITIES:

  • Perform PPA optimization with Fusion compiler.
  • Perform RTL and netlist level Power analysis.
  • Perform post-processing and scripting on report log files for format conversion, data analysis, and information extraction.
  • Setup, run, debug, and analyze reports of ASIC flows (Synthesis, PD, Power, Timing).
  • Implement some blocks at RTL and UPF.
  • Ability to document and communicate clearly.

MINIMUM QUALIFICATIONS:

  • 10+ Years of experience as an ASIC Power engineer, or CAD Engineer/Physical Design engineer.
  • Experience with power estimation tools and synthesis, some physical design.
  • Knowledge of power trade-offs in design and back-end implementation.
  • Hands-on experience in scripting, data analysis.
  • BS in Electrical Engineering/Computer Science or equivalent experience.

Must-Have Skills:

  1. Experience with Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules)
  2. Should know how to use Python, Perl (or similar) scripting, and data-post-processing tools
  3. Experience in low power design, tools and methodologies including power intent UPF specifications
  4. Silicon Power Characterization

Nice-to-have Skills:

  1. Some power profiling experience at IP/SoC level
  2. Experience with Silicon Power Characterization
  3. Experience with Data analytics and visualization

SCREENING QUESTIONS:1. Can you list all the commands required to run PrimePower, including loading the design, reading the vector, and performing a quality check?2. How do you check the name mapping quality in PrimePower/PTPX?3. How can dynamic power be optimized?

For immediate consideration please share your resumes on adarsh.singh@artech.com

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FAQs About Core Engineering - Design Engineer V Jobs at Artech LLC

What is the work location for this position at Artech LLC?
This job at Artech LLC is located in Sunnyvale, CA, according to the details provided by the employer. Some roles may also include multiple work locations depending on the requirement.
What pay range can candidates expect for this role at Artech LLC?
Employer has not shared pay details for this role.
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