Design Engineering Architect

CadenceSan Jose, CA

$136,500 - $253,500 / year

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Overview

Schedule

Full-time

Career level

Senior-level

Remote

On-site

Compensation

$136,500-$253,500/year

Benefits

Health Insurance

Dental Insurance

Vision Insurance

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design Engineering Architect - Roles & Responsibilities

Contribute to PHY architecture development with deep understanding of memory interface PHY IPs (e.g., DDR, LPDDR), including electrical, timing, power, and protocol considerations
Drive architecture decisions aligned with JEDEC standards, protocols, and compliance requirements
Good understanding of PHY/IO circuit architecture including TX/RX, clocking, termination, power delivery, and signal integrity trade‑offs
Act as a customer‑facing technical architect during pre‑sales, evaluations, and post‑delivery support, clearly articulating architecture choices and trade‑offs
Collaborate closely with Sales, Marketing, and Program teams to support customer engagements, RFIs, and technical proposals
Provide expert‑level IP support to customers, including architecture clarification, feature customization
Work cross‑functionally with design, verification, layout, and silicon validation teams to ensure architectural intent is correctly implemented
Review and guide architecture specifications, design reviews, and technical documentation
Influence product and technology roadmap planning by identifying future standards, protocol evolution, and customer‑driven requirements
Demonstrate strong communication, accountability, and technical ownership across internal and external interactions

Required Qualifications

M.S. degree in Electrical Engineering, Computer Engineering, or related field
Minimum 15 years of industry experience in memory interface PHY, high‑speed IO, or related domains
Strong background in memory interface PHYs, JEDEC standards, and protocols
Proven ability to own customer‑facing technical engagements and drive issues to closure
Excellent written and verbal communication skills

The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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FAQs About Design Engineering Architect Jobs at Cadence

What is the work location for this position at Cadence?

This job at Cadence is located in San Jose, CA, according to the details provided by the employer. Some roles may also include multiple work locations depending on the requirement.

What pay range can candidates expect for this role at Cadence?

Candidates can expect a pay range of $136,500 and $253,500 per year.

What employment applies to this position at Cadence?

Cadence lists this role as a Full-time position.

What experience level is required for this role at Cadence?

Cadence is looking for a candidate with "Senior-level" experience level.

What benefits are offered by Cadence for this role?

Cadence offers following benefits: Health Insurance, Dental Insurance, Vision Insurance, Paid Vacation, and 401k Matching/Retirement Savings for this position. Actual benefits may vary depending on the employer's policies and employment terms.

What is the process to apply for this position at Cadence?

You can apply for this role at Cadence either through Sonara's automated application system, which helps you submit applications 10X faster with minimal effort, or by applying manually using the direct link on the job page.