Design Verification Engineer

Pyramid Consulting, IncSan Francisco, CA

$160,000 - $170,000 / year

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Overview

Remote

On-site

Compensation

$160,000-$170,000/year

Job Description

Immediate need for a talented Design Verification Engineer . This is a Fulltime opportunity with long-term potential and is located in San Franscisco, CA(Onsite). Please review the job description below and contact me ASAP if you are interested.Job ID:26-19462Pay Range: $160000 - $170000/annum. Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location).

Key Requirements and Technology Experience:

6+ years of experience with verification concepts and architectures for complex digital and MXS circuits
Experience verifying designs at the block and system levels.
Experience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC)
Experience debugging RTL and gate-level netlists, analyzing schematic diagrams of analog / MXS circuits
Experience using SystemVerilog and advanced verification concepts and methodologies (UVM, SVA)
Experience with Synopsys, Cadence, and Mentor simulations tools
Demonstrated ability to plan and deploy complex, reusable, and scalable verification environments
Experience with Perl/Python and Tcl or other scripting languages
Experience with version control systems (DesignSync, git)
Superior writing, grammar, and verbal communication skills
Excellent problem solver; develops and employs automated processes where applicable
Worked independently and in a global team and dynamic environment in a highly visible role
Possesses ability to learn and adapt to new tools and methodologies on the fly
Must have legal authorization to work in the US.
BS in Electrical Engineering / Computer Engineering and 8+ years of related experience or an MS in Electrical Engineering / Computer Engineering and 6+ years of related experience.
("Design Verification Engineer" OR "Verification Engineer" OR "ASIC Verification Engineer")
And (SystemVerilog OR UVM OR SVA)
And (PLL OR DLL OR ADC OR DAC OR "mixed signal")
And (Synopsys OR Cadence OR Mentor)
And (Python OR Perl OR Tcl)

Our client is a leading IT Industry, and we are currently interviewing to fill this and other similar fulltime positions. If you are interested in this position, please apply online for immediate consideration. Pyramid Consulting, Inc. provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws. By applying to our jobs you agree to receive calls, AI-generated calls, text messages, or emails from Pyramid Consulting, Inc. and its affiliates, and contracted partners. Frequency varies for text messages. Message and data rates may apply. Carriers are not liable for delayed or undelivered messages. You can reply STOP to cancel and HELP for help. You can access our privacy policy here.#Del

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FAQs About Design Verification Engineer Jobs at Pyramid Consulting, Inc

What is the work location for this position at Pyramid Consulting, Inc?

This job at Pyramid Consulting, Inc is located in San Francisco, CA, according to the details provided by the employer. Some roles may also include multiple work locations depending on the requirement.

What pay range can candidates expect for this role at Pyramid Consulting, Inc?

Candidates can expect a pay range of $160,000 and $170,000 per year.

What employment applies to this position at Pyramid Consulting, Inc?

The employer has not provided this information. This may be discussed during the hiring process.

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