Electronic Design Automation (Eda) Engineer
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Overview
Job Description
Position Summary:The Electronic Design Automation (EDA) Engineer will collaborate effectively with cross-functional teams providing design enablement collateral for semiconductor integrated circuit (IC) technologies in addition to providing broad design application support. The EDA engineer will be a significant technical contributor to a broad array of IC development projects, focused on Process Design Kit (PDK) development and release. The ideal candidate will have strong skills in physical verification, Calibre SVRF, LVS, and PEX as well as other semiconductor EDA tools and methodologies. This is a full-time permanent position ideally based in the Minneapolis, Minnesota area, though consideration will be given to remote location.
Major Area of Accountability:
Development,verification, and release of PDK and IP collateral using industry-standard EDA tools.Technical liaison activities between internal teams, design houses, customers, and foundries to ensure successful development, tape-out, and manufacture of customer ICs.Technical support for customers using SkyWater PDKs and IP collateral.Development and enhancement of LVS and PEX extraction decks and design flows.Creation of test cases for verification and validation of LVS and PEX flows.Enablement and improvement of front to back-end IC design flows and manufacturing through PDK development, analysis, validation, and release.Working closely with design, layout, and process engineers to understand and incorporate semiconductor technology requirements into circuit element models and PDKs.
The job also requires performing other duties as assigned. Percentages of time spent on job duties are estimates and may vary for each position.
Required Qualifications:Education: BS or MS in Electrical Engineering or related field.Required Experience and Skills:
10 years of experience in PDK / EDA development and support.Strong understanding of IC technology stack.Experience setting up, testing and supporting LVS and parasitic extraction tools such as Mentor Calibre, Cadence PVS / Quantus, or Synopsys StarRC.Strong understanding of the IP design flow and its requirements, both analog and digital.Fluent in written and spoken English, with excellent technical writing and verbal communication skills.
U.S. Person Required: This position requires compliance with the International Traffic in Arms Regulations (ITAR). All accepted applicants must be U.S. Persons. ITAR defines a U.S. Person as U.S. citizen, U.S. Permanent Resident, Political Asylee, or Refugee.Preferred Qualifications:
Experience directly working with internal and external customers.Experience with 3D IC, interposers , more than Moore technologies.Knowledge and experience with other tools in the IC design flow, spice simulation.Familiarity with parasitic extraction tools such as Mentor Calibre xRC, Cadence Quantus, or Synopsys StarRC.Experience in IP project and/or library management.Familiarity with Tcl and other scripting languages.Proficiency in use of Cadence, Synopsys, or Mentor Graphics EDA software and scripting tasks within.
Proficiency in Linux environment including scripting (Python, etc).Proficient with MS Office and Unix/Linux platforms.
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