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Lead Analog IC Design Engineer

CadenceSan Jose, CA

$119,000 - $221,000 / year

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Overview

Schedule
Full-time
Education
Engineering (PE)
Career level
Senior-level
Remote
On-site
Compensation
$119,000-$221,000/year
Benefits
Health Insurance
Dental Insurance
Vision Insurance

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Role Overview

The Lead Analog IC Design Engineer is responsible for designing and developing analog and mixed-signal circuits- from initial concept and specification through final verification- to ensure conformance with customer requirements.

Required Qualifications

  • At least three years of experience designing and developing CMOS SerDes or high-speed I/O integrated circuits.
  • Design experience with most of the following SerDes circuit blocks: Transmitters and receivers, serializers and deserializers, phase interpolators, low-jitter PLLs, high-speed clock-distribution circuits, bias circuits, and voltage regulators.
  • Good understanding of jitter and signal-equalization techniques.
  • Proficiency with CAD tools for circuit simulation, layout, and physical verification.
  • Master's degree or Ph.D. in electrical engineering.
  • Strong problem-solving skills and analog design aptitude.
  • Clear written and verbal communication skills.
  • Ability to collaborate effectively in a team environment.

Preferred Qualifications

  • Working knowledge of common SerDes standards and their electrical requirements.
  • Experience with Cadence design tools and laboratory testing.
  • Design experience at data rates above 10 Gbps and in process technologies below 28 nm.

The annual salary range for California is $119,000 to $221,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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FAQs About Lead Analog IC Design Engineer Jobs at Cadence

What is the work location for this position at Cadence?
This job at Cadence is located in San Jose, CA, according to the details provided by the employer. Some roles may also include multiple work locations depending on the requirement.
What pay range can candidates expect for this role at Cadence?
Candidates can expect a pay range of $119,000 and $221,000 per year.
What employment applies to this position at Cadence?
Cadence lists this role as a Full-time position.
What experience level is required for this role at Cadence?
Cadence is looking for a candidate with "Senior-level" experience level.
What education level is required for this job?
The education requirement for this position is Engineering (PE). Candidates with relevant qualifications or equivalent experience may also be considered.
What benefits are offered by Cadence for this role?
Cadence offers following benefits: Health Insurance, Dental Insurance, Vision Insurance, Paid Vacation, 401k Matching/Retirement Savings, and Health & Wellness Programs for this position. Actual benefits may vary depending on the employer's policies and employment terms.
What is the process to apply for this position at Cadence?
You can apply for this role at Cadence either through Sonara's automated application system, which helps you submit applications 10X faster with minimal effort, or by applying manually using the direct link on the job page.