S logo

Lead Design Verification Engineer

Automate your job search with Sonara.

Submit 10x as many applications with less effort than one manual application.1

Reclaim your time by letting our AI handle the grunt work of job searching.

We continuously scan millions of openings to find your top matches.

pay-wall

Overview

Schedule
Full-time
Education
Engineering (PE)
Career level
Director
Remote
On-site

Job Description

Job Description

  • Full time, direct hire role at client (semiconductor company)
  • Lead verification efforts on PCIe IPs and SoC products
  • Architect and build system and unit-level UVM verification environment
  • Work with architects to define verification strategy and execution plans
  • Review metrics and deliver task with high quality
  • Analyze Functional, Code, and Test Plan Coverage
  • Drive and participating in Code Reviews
  • Identify, drive, and develop efficiency and IP quality improvement initiatives
  • Drive root cause analysis and corrective actions for Functional bugs found in Silicon
  • Drive projects from start to the finish and conduct Design verification sign-off

Minimal Qualifications

  • Master’s degree in Electrical Engineering or related field
  • 5 years of industrial experience in Design Verification
  • Proficiency in SystemVerilog and Object-Oriented Programming
  • Experience in UVM, SVA, VIP, DPI
  • Understand verification best practices
  • Experience in PCIe protocol stack
  • Proficient scripting language in one of: Python, TCL, Shell, Perl
  • Self-motivated team worker

Preferred Qualifications

  • Experience of overall design verification experience in the ASIC industry
  • Experience in a design verification lead or management role
  • Strong background in the development of verification environments in System Verilog
  • Expertise in constrained random verification methodologies.
  • Formal verification experience a plus
  • Extensive experience verifying complex designs using UVM
  • Experience in CXL, AXI, AHB, USB, I2C, Ethernet

Automate your job search with Sonara.

Submit 10x as many applications with less effort than one manual application.

pay-wall

FAQs About Lead Design Verification Engineer Jobs at SQL Pager

What is the work location for this position at SQL Pager?
This job at SQL Pager is located in San Jose, California, according to the details provided by the employer. Some roles may also include multiple work locations depending on the requirement.
What pay range can candidates expect for this role at SQL Pager?
Employer has not shared pay details for this role.
What employment applies to this position at SQL Pager?
SQL Pager lists this role as a Full-time position.
What experience level is required for this role at SQL Pager?
SQL Pager is looking for a candidate with "Director" experience level.
What education level is required for this job?
The education requirement for this position is Engineering (PE). Candidates with relevant qualifications or equivalent experience may also be considered.
What is the process to apply for this position at SQL Pager?
You can apply for this role at SQL Pager either through Sonara's automated application system, which helps you submit applications 10X faster with minimal effort, or by applying manually using the direct link on the job page.