PCIe Protocol Engineer (Tech Staff Engineer)
SQL PagerSan Jose, California
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Overview
Schedule
Full-time
Career level
Senior-level
Remote
On-site
Job Description
The Candidate will be an expert with 32Gbps SERDES (Serializer/Deserializaer) based protocols, and must possess recent work experience with PCIe Rev.3, 4 and 5 protocol
Minimum Qualifications:
1. BSEE / BSCS with 10+ years of experience.2. Knowledge of FPGA architectures is a must3. Possess an in-depth understanding of hardware architectures, system level IC design implementation, and knowledge of how to create end use scenarios4. Strong technical background in FPGA prototype emulation, and debug5. Strong technical background in silicon validation, failure analysis and debug6. Excellent Board level debug capabilities in lab environment: hands-on troubleshooting skills for digital logic and analog circuit on PCB’s using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Synopsys Identify, Xilinx Chipscope, Altera Signalscope, Lattice Reveal)7. Design with RTL coding in Verilog and VHDL is a must8. Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools9. Good knowledge of validating system level designs based on embedded processors and peripherals such as SPI, I2C, UART, Ethernet, PCI and USB10. Familiarity with the bring up and on-board debug of 32Gbps SERDES11. Hands-on systems level design and debug experience with following high-speed serial communications protocols (must: PHY, PCS and Data link layer of the OSI protocol stack; desirable: transaction and upper layers of the OSI protocol):a. PCIe Gen3/4/512. Experience with the PCI-SIG Compliance Testsa. Protocol Testingb. PCI-CV Testingc. PHY Testing13. Experience with the PCIe Lab Equipmenta. PCIe Analyzerb. PCIe Exerciser14. Strong commitment to quality and customer satisfaction15. Excellent verbal and written communication skills in English16. Able to travel 0-2 times annually if required.
Preferred qualifications:
1. Familiarity with any high speed SERDES controllers that make use of 32Gbps PCS, PMA :a. Ethernet 1, 2.5, 5, 10, 25, 40, 50, 100, 200, 400 Gbps, including familiarity with (U)S(X)GMIIb. Interlaken (4.25 to 412.5 Gbps)c. OTN OTUx (2.66 to 131 Gbps), or SONET/SDH OC3/12/48/192d. (E,X,XGS,NG)-PON or 100G-EPONe. Video interfaces SDI-SD/HD/3GHD and SDI (5.94, 11.88Gbps), Displayport (6.48 to 25.92Gbps), HDMI (3.96 to 42.66 Gbps)f. JESD204C (6.375 to 32 Gbps)
2. Design and debug experience for any of the below high-speed serial communications protocols is a plus, but not necessary:a. Hybrid Memory Cubeb. CPRI Rate 1 to 10+c. Serial Rapid IO 4.1d. Firewiree. Litefastf. USB 3.0g. SATA I, II, IIIh. Fiber Channeli. CoaXpress
3. C, C++ or object-oriented programming skills is desirable4. Knowledge and experience in embedded firmware development is desirable5. Good understanding of embedded firmware/software development process is desirable6. Knowledge and experience in JTAG, SVF and 1532 standards and STAPL programming is desirable7. Knowledge of PERL/TCL scripting is desirable
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FAQs About PCIe Protocol Engineer (Tech Staff Engineer) Jobs at SQL Pager
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This job at SQL Pager is located in San Jose, California, according to the details provided by the employer. Some roles may also include multiple work locations depending on the requirement.
What pay range can candidates expect for this role at SQL Pager?
Employer has not shared pay details for this role.
What employment applies to this position at SQL Pager?
SQL Pager lists this role as a Full-time position.
What experience level is required for this role at SQL Pager?
SQL Pager is looking for a candidate with "Senior-level" experience level.
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