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Physical Design - CAD Lead

Efficient ComputerSan Jose, Pennsylvania

$180,000 - $220,000 / year

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Overview

Schedule
Full-time
Education
Engineering (PE)
Career level
Director
Compensation
$180,000-$220,000/year
Benefits
Paid Vacation
Parental and Family Leave
401k Matching/Retirement Savings

Job Description

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution

 Efficient is seeking a CAD Lead - PD flows/infrastructure  to join our growing team. The ideal CAD Lead would have worked on significant portion of the full gamut of Physical Design flows and flow infrastructure (flowtracer etc).  This role is in a newly formed hardware engineering group and is the seed hire for this discipline. You will get to setup CAD flows and infra from scratch and influence and shape this aspect in the future.

This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

  • Drive and develop PD flows, methodology for state of the art finfet and multi patterning  based technologies from scratch in Cadence Tempus or Synopsys Primetime.
  • Help develop repeatable, predictable , design and process agnostic PD flows.
  • Develop state of the art flow infrastructure to enable consistent and rapid design under tight schedule constraints for multiple product lines in the energy efficient edge AI computing market.
  • Work closely with PD team leads to propose and develop end to end build and signoff flows.
  • Build regression frameworks for ensuring high quality flows and achieve hardware engineering vision of spending 90% or more time on actual design tasks and NOT wrestling with tools.
  • Develop collateral quality checking utils to ensure high design efficiency.
  • Develop and deploy a unified environment for specifying all collaterals (stdcell, memory, PDK, hardips…)  and all flow dependencies (cycle time, PVTRC corners, per flow design and process dependent configuration).
  • Work with 3rd party vendor resources and coordinate their work.
  • Continuously work on improving flow consistency and efficiency in the context of multiple product lines.

Required Qualifications

  • Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
  • Strong python other scripting programming skills.
  • Experience in developing workflow orchestration infrastructure or tools for hardware development (Airflow, flowtracer etc)
  • Familiarity with kubernetes and containerization
  • Experience implementing regression frameworks
  • SQL or other database proficiency (MongoDB ..)
  • Intimate knowledge of hardware design workflows for Physical Design and RTL/DV.
  • Excellent scripting skills in TCL, shell and python.

Desired Qualifications & Experience Requirements

  • Experience in full chip RTL/DV and PD flows.
  • Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology and its implications to physical design
  • Proficiency with industry-grade physical design flow and hands-on building CAD flow infrastructure for PD engineers.
  • Definition of design constraints for static timing analysis (synthesis, pre/post‑cts, sign‑off) and corners/voltage definitions.
  • Experience in integrating analog or mixed-signal macro on top-level design.
  • Experience in verifying IP collaterals.

We offer a competitive salary for this role, generally ranging from $180,000 to $220,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

Why Join Efficient?

Efficient offers acompetitive compensation and benefits package, including401K match, company-paid benefits, equity program, paid parental leave, and flexibility. We are committed to personal and professional development and strive to grow together as people and as a company.

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FAQs About Physical Design - CAD Lead Jobs at Efficient Computer

What is the work location for this position at Efficient Computer?
This job at Efficient Computer is located in San Jose, Pennsylvania, according to the details provided by the employer. Some roles may also include multiple work locations depending on the requirement.
What pay range can candidates expect for this role at Efficient Computer?
Candidates can expect a pay range of $180,000 and $220,000 per year.
What employment applies to this position at Efficient Computer?
Efficient Computer lists this role as a Full-time position.
What experience level is required for this role at Efficient Computer?
Efficient Computer is looking for a candidate with "Director" experience level.
What is the process to apply for this position at Efficient Computer?
You can apply for this role at Efficient Computer either through Sonara's automated application system, which helps you submit applications 10X faster with minimal effort, or by applying manually using the direct link on the job page.