Principal Analog IC Design Engineer, High Speed Serdes

CadenceSan Jose, CA

$136,500 - $253,500 / year

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Overview

Schedule

Full-time

Career level

Senior-level

Compensation

$136,500-$253,500/year

Benefits

Health Insurance

Dental Insurance

Vision Insurance

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Principal Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.

Candidate's background should include a minimum of 7 years of experience in CMOS SerDes or high-speed I/O IC design and development
Working knowledge of a set of common SerDes standards and their electrical requirements is a plus
Must have a thorough understanding of jitter and signal equalization techniques
Proficient design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; ADC and DAC; Bias and Bandgap; and Voltage Regulators
Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment
Position requires proficiency in using CAD tools for circuit simulation, layout, and physical verification
Cadence tool experience, lab test experience, and design experience at >10Gbps and in
MS or PhD in EE

The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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FAQs About Principal Analog IC Design Engineer, High Speed Serdes Jobs at Cadence

What is the work location for this position at Cadence?

This job at Cadence is located in San Jose, CA, according to the details provided by the employer. Some roles may also include multiple work locations depending on the requirement.

What pay range can candidates expect for this role at Cadence?

Candidates can expect a pay range of $136,500 and $253,500 per year.

What employment applies to this position at Cadence?

Cadence lists this role as a Full-time position.

What experience level is required for this role at Cadence?

Cadence is looking for a candidate with "Senior-level" experience level.

What benefits are offered by Cadence for this role?

Cadence offers following benefits: Health Insurance, Dental Insurance, Vision Insurance, Paid Vacation, 401k Matching/Retirement Savings, and Health & Wellness Programs for this position. Actual benefits may vary depending on the employer's policies and employment terms.

What is the process to apply for this position at Cadence?

You can apply for this role at Cadence either through Sonara's automated application system, which helps you submit applications 10X faster with minimal effort, or by applying manually using the direct link on the job page.