Overview
Schedule
Full-time
Education
Engineering (PE)
Career level
Senior-level
Remote
On-site
Job Description
Principal DFT Engineer Celero Communications is seeking a talented DFT Engineer to join our silicon engineering organization. This individual will partner with design, verification, physical design, product, and manufacturing teams to implement robust Design-for-Test methodologies that enable high-quality, high-volume production of complex ASIC and SoC products. What You Will Do• Develop and implement DFT architecture for ASIC and SoC designs.• Perform scan insertion, scan chain planning, and scan compression implementation.• Generate and validate ATPG patterns and analyze fault coverage results.• Implement and verify MBIST, and other on-chip test features.• Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration.• Support JTAG and boundary-scan implementation and debug.• Drive DFT signoff activities and manufacturing test readiness.• Participate in silicon bring-up, failure analysis, and yield improvement efforts. What You Will Bring• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.• 8+ years of ASIC/SoC DFT experience.• Strong understanding of scan, ATPG, fault models, and test coverage methodologies.• Experience with Synopsys TestMAX/TetraMAX, DFT Compiler, Siemens Tessent, Cadence Modus, or equivalent tools.• Knowledge of Verilog/SystemVerilog and digital design fundamentals.• Experience in Linux and scripting using Python, Tcl, Perl, or Shell.• Results-driven engineer with strong debugging abilities.• Comfortable working in fast-paced cross-functional environments.• Passion for delivering high-quality silicon products. Preferred Qualifications• Experience with advanced-node semiconductor technologies.• Hands-on experience with MBIST, compression architectures, and JTAG.• Knowledge of timing closure, physical design impacts, and low-power design techniques.• Experience supporting silicon validation and manufacturing production ramps.• Strong communication and cross-functional collaboration skills. celerocatsone
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FAQs About Principal Design-for-Test (DFT) Engineer Jobs at Celero Communications
What is the work location for this position at Celero Communications?
This job at Celero Communications is located in Irvine, California, according to the details provided by the employer. Some roles may also include multiple work locations depending on the requirement.
What pay range can candidates expect for this role at Celero Communications?
Employer has not shared pay details for this role.
What employment applies to this position at Celero Communications?
Celero Communications lists this role as a Full-time position.
What experience level is required for this role at Celero Communications?
Celero Communications is looking for a candidate with "Senior-level" experience level.
What education level is required for this job?
The education requirement for this position is Engineering (PE). Candidates with relevant qualifications or equivalent experience may also be considered.
What is the process to apply for this position at Celero Communications?
You can apply for this role at Celero Communications either through Sonara's automated application system, which helps you submit applications 10X faster with minimal effort, or by applying manually using the direct link on the job page.