Astera Labs logo

Principal Design Verification Engineer

Astera LabsSan Jose, CA

$185,000 - $230,000 / year

Automate your job search with Sonara.

Submit 10x as many applications with less effort than one manual application.1

Reclaim your time by letting our AI handle the grunt work of job searching.

We continuously scan millions of openings to find your top matches.

pay-wall

Overview

Schedule
Full-time
Education
Engineering (PE)
Career level
Senior-level
Compensation
$185,000-$230,000/year

Job Description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview Astera Labs is looking for a Principal Design Verification Engineer with a passion for breaking complex designs and developing innovative verification strategies for next-generation AI connectivity ASICs. You'll leverage your deep expertise in SystemVerilog, UVM, and hybrid verification methodologies to ensure the highest quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

In this role, you'll own the full verification lifecycle—from test planning through coverage closure—while collaborating with RTL designers, software teams, and system validation engineers. You'll drive verification of excellence, mentor team members, and contribute to methodology improvements that scale across multiple product lines in a fast-paced, high-impact environment.

Key Responsibilities

  • Verification Strategy & Execution
    • Define and execute comprehensive verification strategies using hybrid directed and constrained-random methodologies with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.
    • Own the full verification lifecycle from test plan development through coverage closure and tape-out sign-off
    • Develop and deploy advanced coverage models to identify verification holes and ensure high-quality silicon
  • Technical Problem Solving
    • Debug complex design issues collaboratively with RTL designers, driving root cause analysis to resolution
    • Implement formal verification techniques to complement simulation-based approaches
    • Develop test sequences and stimulus generation for corner-case coverage
  • Collaboration & Leadership
    • Partner with software and system validation teams to develop and execute test plans on emulation platforms
    • Mentor junior verification engineers and drive best practices across the team
    • Contribute to verification infrastructure improvements and automation initiatives

Basic Qualifications

  • Bachelor's degree in Electrical Engineering; Master's preferred
  • 10+ years of experience verifying and validating complex SoCs for Server, Storage, and/or Networking applications
  • Expert-level proficiency with SystemVerilog/UVM-based verification methodologies
  • Proven ability to develop and execute test plans, stimulus generation, and coverage closure strategies
  • Experience with industry-standard simulators, revision control systems, and regression infrastructure
  • Strong debugging skills with ability to work independently and collaboratively with design teams

Preferred Qualifications

  • Master's degree in Electrical Engineering or related field
  • Experience with Verification IPs for protocols such as PCIe (Gen 5+), CXL, Ethernet, DDR4/5, or similar
  • Proficiency with formal verification methods and tools
  • Working experience with scripting tools (Python/Perl) to automate verification infrastructure
  • Experience with emulation platforms and hardware-software co-verification
  • Background in cache verification or directed test methodologies

Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Automate your job search with Sonara.

Submit 10x as many applications with less effort than one manual application.

pay-wall

FAQs About Principal Design Verification Engineer Jobs at Astera Labs

What is the work location for this position at Astera Labs?
This job at Astera Labs is located in San Jose, CA, according to the details provided by the employer. Some roles may also include multiple work locations depending on the requirement.
What pay range can candidates expect for this role at Astera Labs?
Candidates can expect a pay range of $185,000 and $230,000 per year.
What employment applies to this position at Astera Labs?
Astera Labs lists this role as a Full-time position.
What experience level is required for this role at Astera Labs?
Astera Labs is looking for a candidate with "Senior-level" experience level.
What education level is required for this job?
The education requirement for this position is Engineering (PE). Candidates with relevant qualifications or equivalent experience may also be considered.
What is the process to apply for this position at Astera Labs?
You can apply for this role at Astera Labs either through Sonara's automated application system, which helps you submit applications 10X faster with minimal effort, or by applying manually using the direct link on the job page.