Principal Hardware Design Engineer

Job Title: Principal Hardware Design Engineer- Systems Engineering

Location: Onsite, Santa Clara, CA, US

Department: Engineering / Architecture

Salary: USD $170,000 – $225,000 / yr

Sponsorship: Yes

Relocation: Nationwide

Position Overview

As a Principal Hardware Design Engineer, you will join a foundational Central Engineering business group. This team acts as the core technology hub, providing critical IP utilized across diverse product lines, including Automotive, Storage, Security, and Networking.

In this role, you will be a key member of the printed circuit board (PCB) engineering team, designing cutting-edge boards for multiple cross-functional groups. We pride ourselves on designing chips and boards that are more complex and operate at higher speeds than industry standards. If you are passionate about being on the leading edge of technology, this is the ideal place for you.

What You Can Expect

The Signal Integrity Engineering candidate within our Design Center will have the opportunity to contribute directly to the design, implementation, and checkout of critical SOC validation boards.

Key Responsibilities Include:

• Setting Signal Integrity (SI) specifications and establishing SI implementation guidelines for both internal and external design teams.
• Simulating designs to ensure high-quality, high-performance results.
• Collaborating closely with package design and signal integrity teams to ensure package and board parameters are thoroughly understood and aligned.
• Acting as a vital individual contributor within a diverse hardware and software group that fully owns the development and execution of package and validation board design.

Key Activities & Responsibilities

• Reference Board Design: Design reference boards for PCIe Gen5/6 chips; create enterprise server reference systems utilizing PCIe Gen5 CEM sockets and EDSFF.
• Power & Schematics: Select and implement power schemes (including low-voltage, high-current, multi-phase SMPS); capture schematics and collaborate closely with external PCB layout houses.
• Cross-Functional Collaboration: Partner with the RTL team to understand and implement various features/interfaces; collaborate with SI engineers and chip package vendors for layout and design input.
• Silicon Bring-Up: Participate actively in the bring-up and debugging phases of new chips; establish programming parameters for various memory types.
• Technical Decision-Making: Drive critical decisions regarding reference designs, including the selection of connectors, cables, and components.
• External Ecosystem Support: Partner with external vendors to solve technical challenges and finalize designs; interface directly with customers to assist with or implement their unique designs.

What We Are Looking For (Skills, Experience, and Knowledge)

• High-Speed Design: Proven expertise in high-speed diff pair design and deep knowledge of associated PCB design issues.
• Protocols & Architecture: Hands-on experience with PCIE Gen4 or PCIE Gen5 (PAM-4 compliance); solid understanding of PCIe Protocols and cloud compute systems.
• Validation: Direct experience with reference board design targeted for chip validation.
• Power & Signal Integrity: Strong experience with Power Integrity (PI) analysis and power controller design (low-voltage, high-current, multi-phase SMPS).
• Tools & Infrastructure: Proficiency with SI tools (such as Sigrity, SI Soft, HFSS) and schematic capture/PCB layout environments (Cadence Concept preferred).
• System Design: Familiarity with clock generation, distribution, and general mechanical design concepts.

Role Requirements

• Education & Experience:
• Bachelor's degree in Computer Science, Electrical Engineering, or a related field with 5–10 years of professional experience.
• OR a Master's degree / PhD in Computer Science, Electrical Engineering, or a related field with 3–5 years of professional experience.
• Lead Experience: Demonstrated experience serving as a Lead Signal Integrity Engineer.
• Electromagnetics:Strong fundamental understanding of EM. Proven ability in modeling and analyzing transmission lines, via structures, high-speed connectors, and complex BGA packages.
• Simulation Tools: High proficiency in 2D/3D EM tools (such as Sigrity Suite or Ansys EM) as well as HSPICE.
• Lab Equipment & Protocols: Familiarity with Real-Time scopes, VBA, and TDR; direct experience with the analysis of 25Gbps SERDES.
• Guidance:Experience establishing precise Signal Integrity parameters to successfully guide board routing teams.
• Communication:Customer-facing experience paired with excellent verbal and written communication skills.

Preferred Qualifications (Plusses):

• Working knowledge of ADS, QSI/QDC, or Hyperlynx.
• Experience setting up, executing, and summarizing comprehensive Power Integrity simulations.
• Experience interfacing with characterization teams to ensure design calculations effectively collaborate with implemented board and package results.