Principal PLL Design Engineer
Celero CommunicationsSan Jose, California
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Overview
Schedule
Full-time
Education
Engineering (PE)
Career level
Senior-level
Remote
On-site
Job Description
Principal PLL Design EngineerAbout the job Are you a PLL Design Engineer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI? We are looking for a High-Speed CMOS PLL Analog Design Engineer –who is excited to join a fast-growing Start-Up Company with a key role for expert in clocking circuits for next generation optical transceivers, high-speed SerDes, and ADC/DAC systems. Candidate will have the opportunity to architect and design PLLs for next generation transceivers.What You Will Do Understand trade-offs between different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range Architect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization Supervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies Be responsible for PLL bring up in the lab, conducting performance characterization using state-of-the-art lab equipment Conduct comprehensive system-level simulations and validation for PLL integration into advanced transceiver technologies What You Will Bring Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design, and production level tape-out experience. Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes) • Deep understanding of phase noise analysis, VCO design, LDOs and supporting circuitry associated with PLLs • Proficient in cadence virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system-level modelling • Strong communication and documentation skills Annual Base Salary Range: $2000,000 - $300,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.) celerocatsone
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FAQs About Principal PLL Design Engineer Jobs at Celero Communications
What is the work location for this position at Celero Communications?
This job at Celero Communications is located in San Jose, California, according to the details provided by the employer. Some roles may also include multiple work locations depending on the requirement.
What pay range can candidates expect for this role at Celero Communications?
Employer has not shared pay details for this role.
What employment applies to this position at Celero Communications?
Celero Communications lists this role as a Full-time position.
What experience level is required for this role at Celero Communications?
Celero Communications is looking for a candidate with "Senior-level" experience level.
What education level is required for this job?
The education requirement for this position is Engineering (PE). Candidates with relevant qualifications or equivalent experience may also be considered.
What is the process to apply for this position at Celero Communications?
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