Principal SerDes Design Engineer
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Overview
Schedule
Full-time
Education
Engineering (PE)
Career level
Senior-level
Remote
On-site
Compensation
$200,000-$300,000/year
Job Description
Principal SerDes Design EngineerAbout the job We are looking for a SerDes Lead Designer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI. Candidate will have the opportunity to architect and design SerDes for next generation transceivers.What You Will Do Define architecture, specifications, and circuit topologies for next-generation SerDes Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies and jitter budgeting Design high-performance analog/mixed-signal circuits in advanced node technologies Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab Correlate silicon measurements with simulated data, and lead performance optimization in the system environmentWhat You Will Bring Master’s degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design Proven record of taking high-speed SerDes design to tape-out and volume production Experience in lab bring-up, characterization, and debugging designs that reach out production Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes) • Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs • Strong communication and documentation skills Annual Base Salary Range: $200,000 - $300,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.) celerocatsone
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FAQs About Principal SerDes Design Engineer Jobs at Celero Communications
What is the work location for this position at Celero Communications?
This job at Celero Communications is located in San Jose, California, according to the details provided by the employer. Some roles may also include multiple work locations depending on the requirement.
What pay range can candidates expect for this role at Celero Communications?
Candidates can expect a pay range of $200,000 and $300,000 per year.
What employment applies to this position at Celero Communications?
Celero Communications lists this role as a Full-time position.
What experience level is required for this role at Celero Communications?
Celero Communications is looking for a candidate with "Senior-level" experience level.
What education level is required for this job?
The education requirement for this position is Engineering (PE). Candidates with relevant qualifications or equivalent experience may also be considered.
What is the process to apply for this position at Celero Communications?
You can apply for this role at Celero Communications either through Sonara's automated application system, which helps you submit applications 10X faster with minimal effort, or by applying manually using the direct link on the job page.