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Principal Software Engineer - Low Power Verification

CadenceSan Jose, CA

$136,500 - $253,500 / year

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Overview

Schedule
Full-time
Career level
Senior-level
Compensation
$136,500-$253,500/year
Benefits
Health Insurance
Dental Insurance
Vision Insurance

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Principal Software Engineer - Low-Power Verification (Palladium & Protium)

We are seeking a highly skilled Senior Software Engineer to help build the next generation of low-power verification software for the Palladium and Protium emulation platforms. In this role, you will drive innovations that improve the debuggability, performance, and scalability of multi-billion-gate UPF (Unified Power Format) designs across modular compilation flows (2-state and 4-state).

Key Responsibilities

  • Design, develop, and optimize low-power verification software for Palladium and Protium.

  • Improve UPF design debuggability within the IXCOM Modular Compiler and Parallel Partition Compiler (2-state and 4-state).

  • Enhance compiled streaming probes and accelerate waveform generation for large-scale designs.

  • Collaborate closely with R&D, Product Engineering (PE), and Application Engineering (AE) to deploy UPF solutions across diverse flows, including:

  • AVIP + UPF + 2/4-state

  • UVMA + UPF + 2/4-state

  • MC + UPF

  • Dielets + UPF

  • Consolidate and unify UPF software across Palladium and Protium platforms.

  • Contribute to major initiatives such as:

  • MC + PPC flow with UPF 4-state

  • UPF compilation time optimization

  • Full Vision UPF probe integration

  • SAGE UPF debug with Verisium

Qualifications

  • Bachelor's degree in Computer Science or Electrical Engineering with 7+ years of relevant experience,

OR a Master's degree with 5+ years,

OR a PhD with 1+ year of industry experience.

Required Skills

  • Strong proficiency in object-oriented design and C++ development.
  • Experience with standard C/C++ libraries and the C++ STL.
  • Demonstrated ability to build high-performance software for large-scale data processing.
  • Scripting experience in Perl, Tcl/Tk, and/or Python.
  • Familiarity with IEEE 1801 and UPF implementation.
  • Experience with Verilog, SystemVerilog, and VHDL.

The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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FAQs About Principal Software Engineer - Low Power Verification Jobs at Cadence

What is the work location for this position at Cadence?
This job at Cadence is located in San Jose, CA, according to the details provided by the employer. Some roles may also include multiple work locations depending on the requirement.
What pay range can candidates expect for this role at Cadence?
Candidates can expect a pay range of $136,500 and $253,500 per year.
What employment applies to this position at Cadence?
Cadence lists this role as a Full-time position.
What experience level is required for this role at Cadence?
Cadence is looking for a candidate with "Senior-level" experience level.
What is the process to apply for this position at Cadence?
You can apply for this role at Cadence either through Sonara's automated application system, which helps you submit applications 10X faster with minimal effort, or by applying manually using the direct link on the job page.