Principle Hardware Design Engineer - Systems Engineering

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As a Hardware Design Principal Engineer with Marvell, you'll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You'll be part of the printed circuit board (PCB) engineering team designing boards for many different groups at Marvell. Additionally, Marvell is designing more complex chips and boards than our competitors, for higher speeds than anyone else. We're on the leading edge of this technology and you'll love being a part of this.

What You Can Expect

The Signal Integrity Engineering candidate within the Marlborough Design Center will have opportunity to contribute to design, implementation, and check out of critical SOC validation boards. This includes setting SI specifications, SI implementation guidelines for internal and external design teams, and simulation of the design to ensure high quality results. Additional opportunities include collaboration with the package design and signal integrity teams to ensure package and board parameters are well understood. This role is for an individual contributor who will join a diverse hardware and software group that owns development and execution of package and validation board design and implementation.

What We're Looking For

Skills, Experience, and Knowledge

• High speed diff pair design
• PCIE Gen4 or PCIE Gen5 (PAM-4 okay too)
• Experience with reference board design for chip validation
• Knowledge of PCB design issues associated with high speed diff pair
• Power controller design - low voltage, high current, multi-phase SMPS
• Experience with Power Integrity analysis
• Knowledge of SI tools - Sigrity, SI Soft, HFSS
• Component Selection
• Schematic capture and PCB Layout tools (Prefer Cadence Concept)
• Cloud compute systems
• PCIe Protocols
• Clock generation and distribution
• Familiar with Mechanical design concepts

Activities

• Design Reference board for PCIe Gen5/6 chip.
• Select and implement power scheme
• Capture Schematic
• Work with PCB Layout house
• Create enterprise server reference systems, using PCIe Gen5 CEM sockets, and EDSFF.
• Work with customers to assist with their designs, and/or implement their designs.
• Work with RTL team to understand and implement various features and interfaces.
• Provide for programming of various memories
• Participate in bring and debug of chips.
• Make decisions about reference designs, including connectors, cables.
• Work with external vendors for problems, and completing their designs.
• Work with SI engineers.
• Work with chip package vendor for package design input

Requirements:

• Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience.Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
• Experience as Lead Signal Integrity Engineer.
• Strong understanding of EM fundamentals. Modeling and analysis of transmission lines, via structures, high-speed connectors, and complex BGA packages.
• Proficiency in 2D/3D EM tools such as Sigrity Suite or Ansys EM as well as HSPICE.
• Familiarity with Real-Time scope, VBA, TDR.
• Experience with analysis of 25Gbps SERDES.
• Experience establishing Signal Integrity parameters to guide board routing team.
• Customer facing experience with strong verbal and written communication skills.
• Working knowledge of ADS, QSI/QDC, or Hyperlynx is a plus.
• Experience setting up, running, and summarizing Power Integrity simulations is a plus.
• Experience interfacing with characterization team to ensure design calculations can be collaborated with implemented board and package results is a plus.

Expected Base Pay Range (USD)

150,680 - 225,700, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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