Intel Corp. logo

RTL Design Engineer

Intel Corp.Austin, TX

$105,650 - $200,340 / year

Automate your job search with Sonara.

Submit 10x as many applications with less effort than one manual application.1

Reclaim your time by letting our AI handle the grunt work of job searching.

We continuously scan millions of openings to find your top matches.

pay-wall

Overview

Schedule
Full-time
Education
Engineering (PE)
Career level
Senior-level
Remote
On-site
Compensation
$105,650-$200,340/year
Benefits
Health Insurance
Paid Vacation
401k Matching/Retirement Savings

Job Description

Job Details:

Job Description:

Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs. Participates actively in the definition of architecture and microarchitecture features of the CPU being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Documents micro architectural specs (MAS) of the CPU features being designed. Supports SoC customers to ensure highquality integration of the CPU block.

Qualifications:

Minimum Qualifications • The candidate must have a Bachelor's Degree in Electrical or Computer Engineering or any STEM related education with at least 2+ years of experience -OR- Master's Degree in Electrical or Computer Engineering • At least 1+ years of coursework or experience in the following areas: o Basic Logic Design o Microprocessors o Computer Architecture o Digital design and RTL coding o Verilog/SystemVerilog and/or VHDL o Synthesis tools (Design Compiler, Genus) o Scripting languages (Python, Perl, TCL) Preferred Qualifications • Experience with advanced verification methodologies (UVM, OVM) • Knowledge of low-power design techniques • Understanding of physical design constraints and timing closure • Experience with version control systems (Git, Perforce) • Experience with simulation tools (ModelSim, VCS, Xcelium)

Job Type:

College Grad

Shift:

Shift 1 (United States of America)

Primary Location:

US, Texas, Austin

Additional Locations:

US, Arizona, Phoenix, US, Oregon, Hillsboro

Business group:

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $105,650.00-200,340.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

  • ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Automate your job search with Sonara.

Submit 10x as many applications with less effort than one manual application.

pay-wall

FAQs About RTL Design Engineer Jobs at Intel Corp.

What is the work location for this position at Intel Corp.?
This job at Intel Corp. is located in Austin, TX, according to the details provided by the employer. Some roles may also include multiple work locations depending on the requirement.
What pay range can candidates expect for this role at Intel Corp.?
Candidates can expect a pay range of $105,650 and $200,340 per year.
What employment applies to this position at Intel Corp.?
Intel Corp. lists this role as a Full-time position.
What experience level is required for this role at Intel Corp.?
Intel Corp. is looking for a candidate with "Senior-level" experience level.
What education level is required for this job?
The education requirement for this position is Engineering (PE). Candidates with relevant qualifications or equivalent experience may also be considered.
What benefits are offered by Intel Corp. for this role?
Intel Corp. offers following benefits: Health Insurance, Paid Vacation, 401k Matching/Retirement Savings, and Health & Wellness Programs for this position. Actual benefits may vary depending on the employer's policies and employment terms.
What is the process to apply for this position at Intel Corp.?
You can apply for this role at Intel Corp. either through Sonara's automated application system, which helps you submit applications 10X faster with minimal effort, or by applying manually using the direct link on the job page.