Overview
Schedule
Full-time
Career level
Senior-level
Remote
On-site
Job Description
Job Responsibilities• To help develop an ASIC for our automotive and Data Center artificial intelligence computing architecture• Participating in Architecture definition and modeling, verification test plan and testbench.• Developing the micro-architecture specification, RTL in Verilog/System Verilog, performance/speed/power goals.• Bring up the chip in lab, composing bring-up scripts.• Collaborate with verification, software and system teams to ensure a successful product delivery.
Required Skills• MS with 10+ years or PhD with 8+ years, 5+ years in ASIC design team lead.• Experience in logic design on high-performance data center chip and integration of acquired IP blocks• Good knowledge on ASIC design and verification methodologies and flows• Hand-on experience: System Verilog, C++, Perl/Python, UVM, Synthesis, Formal Verification, Static Timing Analysis• Experience with processor design, AI/Deep Learning, PCIe/DDR, FPGA emulation• Proven track record as ASIC design on several production tape-outs• Excellent written and verbal interpersonal skills
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FAQs About Senior ASIC Design Engineer Jobs at SQL Pager
What is the work location for this position at SQL Pager?
This job at SQL Pager is located in Sunnyvale, California, according to the details provided by the employer. Some roles may also include multiple work locations depending on the requirement.
What pay range can candidates expect for this role at SQL Pager?
Employer has not shared pay details for this role.
What employment applies to this position at SQL Pager?
SQL Pager lists this role as a Full-time position.
What experience level is required for this role at SQL Pager?
SQL Pager is looking for a candidate with "Senior-level" experience level.
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