Senior / Staff System Validation Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description

• Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers' system requirements in the highest regard and is solely responsible for certifying a product's conformance to this high bar.
• Understand the performance and functionality requirements our AI fabric Switches must deliver to enable customers developing Data Center systems using Astera Labs' game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
• Formulate a comprehensive validation plan for AI fabric switch products. automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion.
• Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs' solutions.

Basic Qualifications 

• Strong academic and technical background in Electrical or Computer Engineering. At a minimum, a Bachelor's is required, and a Master's is preferred.
• ≥3 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Basic understanding of x86/ARM architecture, UEFI/Linux boot sequence. 
• Good understanding of High Speed Signaling Principles.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!

Required Experience 

• Hands-on, thorough knowledge of high-speed protocols like  PCIe, CXL, NVMe, or Ethernet.
• Experience with Silicon/System bring-up, validation, and debug experience, including in customer systems.
• A strong background in developing bench automation techniques, especially using Python, with emphasis on execution efficiency, repeatability, data analysis and reporting.
• Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites.
• Ability to work on multiple projects.

Preferred Experience 

• Working knowledge of C or C++ for embedded FW and device drivers.
• Familiarity with PCIe compliance standards and ability to follow and be involved in compliance consortiums to adapt the tests to be run from X86/ARM based platforms.
• Knowledge of schematic capture and PCB layout tools from Cadence Allegro, Altium, etc.
• Exceptional interpersonal and collaboration skills, with a proven track record of effectively leading, influencing, and navigating complex matrixed environments.

Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $135,000 USD - $165,000 USD for Senior Level, and $160,000 USD - $195,000 USD for Staff Level.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.