Senior Design Verification Engineer

This Jobot Job is hosted by: Alex LuhrsenAre you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume.Salary: $150,000 - $200,000 per yearA bit about us:We are seeking a dedicated and detail-oriented Quality Technician to join our team. As a Quality Technician, you will play a critical role in ensuring the highest standards of quality in the manufacturing and assembly of cutting-edge electronics and components. This position will require you to collaborate closely with various teams to drive improvements and ensure products meet strict specifications and functional requirements.Why join us?premiere medical, dental, vision, and life insurance plans401kInclusive, flexible work environment. We offer healthy snacks and daily catered meals, in addition to family-friendly company events featuring our CEO’s famous BBQ!Job DetailsAbout the RoleJoin a world-class team building the next generation of high-performance compute hardware for artificial intelligence and machine learning applications. We’re developing industry-leading AI accelerators that push the limits of scale, speed, and efficiency—empowering researchers and enterprises to train and deploy the largest AI models with unprecedented ease.As a Senior Design Verification Engineer, you’ll own the end-to-end verification of a critical subsystem in our next-generation AI processor. You’ll collaborate with experts across architecture, RTL design, physical design, firmware, and validation to ensure flawless execution from concept to post-silicon bring-up.This is a high-impact role where your technical insight, leadership, and creativity will directly shape the success of our products.Key ResponsibilitiesOwn and drive the full verification lifecycle for a major IP block—from initial strategy through post-silicon validation.Define and implement advanced verification methodologies, test plans, and coverage metrics that ensure top-tier quality and performance.Develop and maintain UVM-based, constrained-random and directed testbenches.Collaborate closely with architecture and design teams to review specifications and ensure functional correctness and testability.Debug complex issues spanning simulation, emulation, and silicon.Enhance verification infrastructure and flows for improved scalability, coverage, and turnaround time.Mentor and guide junior engineers, promoting best practices and technical excellence.Provide clear communication and technical leadership on progress, risks, and schedules across teams.Qualifications10+ years of design verification experience in complex ASIC/SoC projects.Deep proficiency in SystemVerilog and UVM.Strong understanding of verification planning, coverage closure, and constrained-random methodologies.Experience with industry-standard EDA tools, simulators, and debugging environments.Skilled in scripting languages (Python, Perl, or similar) for automation and productivity.Demonstrated success in cross-functional collaboration and problem-solving.Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.Preferred ExperienceVerification of memory controllers, high-performance interconnects, or compute subsystems.Exposure to emulation, FPGA prototyping, or post-silicon bring-up.Contributions to developing scalable, reusable verification environments and methodologies.Proven ability to influence verification strategy and mentor others in advanced techniques.Interested in hearing more? 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