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Senior Development Test Engineer — Pre & Post-Silicon Software Test, Validation and Characterization

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Overview

Schedule
Full-time
Education
Engineering (PE)
Career level
Senior-level
Remote
On-site

Job Description

About the role

We are seeking an experienced to own the end-to-end testing, characterization, and failure analysis strategy for complex, next-generation multi-die packages.

You will own the complete validation lifecycle across a multi-die architecture—covering high-speed die-to-die (UCIe) interconnects, Power Delivery Networks (PDN/PMIC), Platform Management Controllers (PMC), PCIe/CXL subsystems.

Additionally, you will apply statistical analysis and machine learning to test data—driving outlier detection, bench-to-ATE correlation, and predictive telemetry signals—without treating ML models as a substitute for true physical root-cause analysis.

What you’ll do

Test content and automation

  • Test Plan Ownership: Define development test strategies, coverage targets, content architecture, and strict traceability from architectural requirements to validation evidence.
  • Bare-Metal & C/Python Test Content: Write low-level C and Python test suites—including bare-metal exercisers, traffic generators, stress patterns, and custom firmware drivers/hooks.
  • Scalable Automation & HIL: Build robust test frameworks featuring instrument control, automated sequencing, structured result capture, and Hardware-in-the-Loop (HIL) CI/CD integration for continuous validation.
  • Bench-to-ATE Handoff: Develop lab-to-ATE correlation test suites and drive smooth handoffs to Product & Test Engineering (PTE)
  • Own the development test plan: coverage goals, content architecture, and the traceability between a requirement, the test that exercises it, and the evidence it passed.

Characterization and margin

  • Injection Frameworks: Build minimally invasive fault-injection hardware/software infrastructure that perturbs target datapaths without destabilizing the test setup itself.
  • Protocol & Platform Fault Testing: Execute rigorous error campaigns targeting CRC retries, lane degradation/repair, sideband timeouts, PCIe AER, DMA/IOMMU translation faults, and PMIC reset conditions.
  • Firmware & Resilience Testing: Validate system firmware error handlers, watchdog timers, and hardware-level fault containment behavior under out-of-spec conditions.

Required qualifications

  • Experience: 8–10+ years in post-silicon validation, system software testing, silicon bring-up, or development test for complex SoCs / ASICs / GPUs.
  • Software/Firmware Skills: Advanced proficiency in C and Python for low-level bare-metal test content, hardware abstraction, and automation frameworks.
  • Silicon Characterization: Proven experience with Shmoo plotting PVT corner testing, jitter/margin analysis, and guard-band definition.
  • Fault Injection Expertise: Hands-on experience building or executing error-injection and recovery validation campaigns on production silicon.
  • Lab Instrumentation: Fluency with oscilloscopes, protocol analyzers (PCIe/CXL), logic analyzers, BERTs, thermal chambers, controllable power supplies, and JTAG debuggers.
  • High-Speed & System Protocols: Practical, protocol-level understanding of high-speed serial interfaces (PCIe, CXL, or UCIe) and control buses (I2C, SPI, UART, PMBus, SMBus).
  • Power Systems: Solid grasp of system power delivery—including sequencing, PMIC telemetry, DVFS, voltage regulation, and protection trip limits.
  • Data & Tooling: Competency with toolchains (Git, CMake, GCC/Clang, CI pipelines) and statistics/data analysis over test populations.
  • Education: BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
  • AI Tool usage : AI coding and automation tool is must for this role

Compensation

The compensation range shown below represents total target cash compensation and includes both base salary and target bonus. Actual compensation will vary based on factors such as experience, skills, qualifications, job level, and work location.

In addition to cash compensation, this position is eligible for equity in the form of stock options, giving you the opportunity to share in the Company’s long-term growth and success.

Automate your job search with Sonara.

Submit 10x as many applications with less effort than one manual application.

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FAQs About This Job

What is the work location for this position at TYLsemi?
This job at TYLsemi is located in San Jose, California, according to the details provided by the employer. Some roles may also include multiple work locations depending on the requirement.
What pay range can candidates expect for this role at TYLsemi?
Employer has not shared pay details for this role.
What employment applies to this position at TYLsemi?
TYLsemi lists this role as a Full-time position.
What experience level is required for this role at TYLsemi?
TYLsemi is looking for a candidate with "Senior-level" experience level.
What education level is required for this job?
The education requirement for this position is Engineering (PE). Candidates with relevant qualifications or equivalent experience may also be considered.
What is the process to apply for this position at TYLsemi?
You can apply for this role at TYLsemi either through Sonara's automated application system, which helps you submit applications 10X faster with minimal effort, or by applying manually using the direct link on the job page.