Sram Circuit Design Intern, MS - Summer 2027

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell's Central Engineering Foundational IP team is looking for a motivated SRAM Circuit Design Intern to join us in Burlington, VT. You'll work hands-on as part of a team designing, verifying, and characterizing high-performance memory used in cutting-edge semiconductor technologies. This role is an incredible opportunity to apply your digital and analog circuit design fundamentals while collaborating with experienced engineers on real-world products that are deployed at scale.

About the Position:

Are you ready to use your engineering background to innovate and deliver the data infrastructure technology that connects the world and enables the powerful AI tools that are revolutionizing our industry? The Central Engineering Memory Development team designs and implements cutting edge memory solutions for state-of-the-art ASICs and business units within Marvell. As a member of the Memory Development team you will join a select group of engineers working in the world's most advanced process technologies and forge the way for industry leading chip design. The team designs custom SRAM compilers, hardware security IP, and software to guide System on Chip (SoC) memory usage in advanced Gate All Around (GAA) and FinFET semiconductor nodes.

This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.

What You Can Expect

• Design and implement custom digital circuits optimizing Power, Performance, and Area metrics (PPA)
• Schematic entry (Cadence Virtuoso), Circuit Simulation (Spectre, MDL), Verification (Verilog, VHDL)
• Statistical analysis of complex circuits across a wide Process, Voltage and Temperature range
• Process and visualize data using scripting tools (Perl, Python, Copilot)
• Verilog test pattern generation, simulation and waveform debug for large, complex memory designs
• Analyze, summarize, document, and present results to stakeholders to justify design approaches

What We're Looking For

• Currently pursuing a Master's Degree in Electrical Engineering or a related field with an expected graduation date between Fall 2027 - Summer 2028

Preferred Qualifications:

• Familiarity working in a Unix/Linux environment

• Understanding of analog or digital memory circuits

• Strong Programming Skills in common scripting languages

• Previous exposure to Cadence design tools

• Ability to work independently with regular check-ins and team support

• Strong verbal and written communication skills

Expected Base Pay Range (USD)

35 - 69, $ per hour.

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights for our interns: medical, dental, and vision coverage, perks and discounts, robust mental health resources to prioritize emotional well-being, and paid holidays. Additional compensation may be available for intern PhD candidates. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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