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Senior/Principal ASIC Digital Design Engineer
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Job Description
- Competitive Pay
- Flexible Work Schedule
- Health Benefits and Insurance
- Retirement fund contributions
- Profit Sharing
- Generous Paid Time Off Policy
- Collaborate with team leaders to explore and clearly identify real problems and solutions.
- Develop and define the microarchitecture of new Idaho Scientific IP to optimize performance, I/O, power consumption, area utilization, recurring cost and security functions.
- Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages.
- Integrate complex systems that instantiate both Idaho Scientific and third party IP.
- Contribute to all aspects of design success from specification to production.
- Apply our state-of-the-art IP to ASIC and FPGA products in the real world.
- Define and improve high-quality design methods and processes.
- Mentor and guide other ASIC design engineers.
- US Citizenship (no exceptions)
- Proven work experience designing and fabricating an ASIC (no exceptions)
- Ability to get a security clearance
- Solid technical background with at least 5 years of experience in FPGA or ASIC product development
- Ability to communicate clearly in person and in written documentation
- Degree in Computer Engineering, Computer Science, Electrical Engineering or related field
- In-depth knowledge and experience with digital architectures and design methods such as RTL coding, synthesis, place-and-route, timing closure, constrained-random and formal verification
- Strong analytical and problem solving skills
- Extreme attention to detail
- A willingness to roll up one’s sleeves to get the job done
- Skilled at working effectively with cross functional teams
- US Security Clearance, Active or current within the last two years
- In-depth understanding of microprocessor architectures
- Working knowledge of applied cryptography and cyber security topics
- Experience applying principles of cyber security to operational technology and embedded systems
- Experience with SystemVerilog, VHDL, and Test-Driven Development principles
- The preferred work location is at Idaho Scientific headquarters in Boise, Idaho or in Salt Lake City, Utah
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