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Job Details:

Job Description:

About Altera

At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

Altera is seeking a highly motivatedSenior Physical Design Engineerto join our Physical Design organization. In this role, you will be responsible for implementing custom IP and SoC designs from RTL through GDSII, driving physical implementation, timing closure, power optimization, and design signoff for next-generation FPGA products. You will collaborate closely with RTL designers, Design Verification, DFT, Timing, and CAD teams to deliver high-quality silicon while contributing to the continuous improvement of physical design methodologies and automation.

This role is ideal for an engineer with strong experience across the complete physical implementation flow who enjoys solving complex timing, power, and physical design challenges in advanced process technologies.

Responsibilities

• Perform physical design implementation of custom IP and SoC designs from RTL through GDSII to create a manufacturing-ready design database.

• Execute all aspects of the physical design flow, including synthesis, floorplanning, place and route, clock tree synthesis (CTS), static timing analysis (STA), power and clock distribution, reliability analysis, and power/noise analysis.

• Perform physical verification and design signoff, including formal equivalence checking, static timing verification, reliability verification, power integrity analysis, layout verification, electrical rule checking (ERC), and structural design checking.

• Analyze implementation and signoff results, identify violations, and develop solutions that improve current and future product architectures.

• Apply expertise in physical clock design, timing closure, placement, routing, synthesis, DFT implementation, multiple power domain analysis, and coverage analysis using industry-standard EDA tools.

• Optimize physical designs to improve power, performance, frequency, and area (PPA).

• Collaborate with cross-functional engineering teams to resolve implementation challenges throughout the design cycle.

• Participate in the development and continuous improvement of physical design methodologies, design flows, and automation.

What You'll Bring

• Strong analytical and problem-solving skills with the ability to debug complex physical implementation challenges.

• Excellent collaboration and communication skills within cross-functional engineering teams.

• Ability to manage multiple technical priorities in a fast-paced development environment.

• Passion for delivering high-quality silicon and continuously improving design methodologies.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$133,200 - $192,825 USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

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Qualifications:

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.

• 6+ years of hands-on experience with digital ASIC or SoC physical design implementation.

• 6+ years of experience performing RTL-to-GDSII physical design flows.

• 6+ years of experience with synthesis, floorplanning, place and route, and clock tree synthesis (CTS).

• 6+ years of experience performing static timing analysis (STA) and timing closure.

• 4+ years of experience with physical verification, including DRC, LVS, ERC, and signoff methodologies.

• 4+ years of experience using industry-standard physical design EDA tools such as Synopsys Fusion Compiler, ICC2, PrimeTime, Cadence Innovus, or equivalent.

• 3+ years of experience optimizing designs for power, performance, and area (PPA).

• 2+ years of experience supporting designs with multiple voltage or power domains.

Preferred Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

• Experience with advanced semiconductor process nodes (7nm, 5nm, 3nm, or similar).

• Experience implementing DFT-aware physical design flows and scan chain optimization.

• Experience with physical design automation, scripting, and methodology development using Python, Tcl, Perl, or Shell.

• Experience working on large-scale SoC or FPGA architectures.

• Familiarity with power integrity, IR drop, electromigration (EM), and signal integrity analysis.

• Experience collaborating across architecture, RTL, timing, DFT, verification, and CAD teams in a high-volume product development environment.

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

San Jose, California, United States

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.