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SoC Top-Level& block-levelPhysical Design Engineer

As ablock-level andtop-levelSOCPhysical Design Engineer, you will contribute to all phases of physical design from RTL to the delivery of our final GDSII. Your responsibilities include:

Responsibilities:

• Implement physical design at thelargeSoC chip level from RTL to GDSII, creating a design database ready for manufacturing.

• Interact with IP vendors to understand IP integration requirements and integrate all blocks, IPs, andsub-chipsat a large SoC level.

• Collaborate with the packaging team onMicrobump/Probe Bump/Bump/Pad placement.

• Build full chip floorplan, including pads/ports/bump placement, block placement and optimization, block pins placement and alignment, power grid, and RDL design, etc.

• Develop the chip-level clock network and clock stations in collaboration with clock experts.

• Budget timing among blocks andsub-chipsat the chip level, generating block/chip-level static timing constraints.

• Arrange, analyze, andoptimizefeedthrough and repeaters among all blocks/sub-chipsat the chip level.

• Perform block-level place and route,including customplace & route,ensuring the design meets timing, area, power constraints, and all sign-off criteria.

• Generate and implement ECOs to fix timing, signal integrity, EM/IR violations, PV, and complete formal verification.

• Integrate DFT into physical design, ensuring alignment with overall test strategies and manufacturing requirements.

• Run Physical Design verification flow at chip/block level, fixing LVS/DRC/ERC/ANT violations.

• Collaborate closely with architecture, frontend design, DV, and package teams to ensure cohesive design implementation and successful projecttapeouts.

Minimum Qualifications:

Education:

• BS degree in electrical engineering, computer engineering, or a related field with 7+ years of experience in block or full-chip physical design, or

• MS degree in the above fields with 5+ years of related experience.

Technical Expertise:

• Deep design experience in large SoC designs, including IP integration,padringdesign, bump planning, and RDL routing strategy.

• Extensive knowledge and practices in Physical Design, including physically aware synthesis, floor-planning, place & route, CTS, and repeater/feedthrough.

• Experience in developing and implementing power-grid and clocknetworkat chip level.

• Knowledge of basic SoC architecture and HDL languages like Verilog to work with the logic design team for timing fixes.

• Experience in physical design verification to debug LVS/DRC/ERC/ANT issues at chip/block level.

• Experience in custom place and route.

• Exposure to 2.5D/3D packaging is preferred.

• High performance and large chip design experienceispreferred.

• Exposure to DFT is preferred.

• Proficiencyin writing Linux shell scripts in Perl, TCL, and Python.

• Real chiptapeoutexperiencein7nm and/or below with a successful signofftrack record.

• Self-motivated with strong problem-solving and debugging skills.

• Ability to work effectively in a dynamic group environment.