Ui Ux Design Jobs 2026 (Now Hiring) – Smart Auto Apply

3-year contract an ASIC and FPGA RTL Design Engineer (Hardware Engineer). Pay Range: $90-$110/hr. Hybrid: 3 days onsite with more flex later on Clearance: eligible to get Secret The Tactical Networks Group specializes in advanced network and communications systems development, with a focus on rapid prototyping of ASICs to support radical next generation tactical mobile, military airborne communications systems. The group is seeking a strong ASIC and FPGA RTL design engineer with 10+ years of experience. The Tactical Networks Group is seeking to hire a hardware engineer with 10 years of experience working on different aspects of ASIC design and FPGA design for a high-throughput, low-power signal processing for a communications applications. The candidates for these positions must have experience working independently and part of a team on complex ASIC design and multi-FPGA emulations. The candidate must be able to develop new RTL modules with minimum supervision. Required Skills: 1.Hardware architecture design and verification 2.VHDL/Verilog design and verification expertise 3.ASIC/FPGA design and verification expertise 4.Xilinx Virtex/Kintex 7 and/or UltraScale/Ultrascale+ experience 5.Vivado/Modelsim workflow development experience 6.Signal processing digital circuit design 7.Integration of 3rd party IP 8.Board-level interface debugging and verification 9.Ability to write unit-level and system-level verification test cases Preferred Skills: 1.Working with Ethernet/Serdes IP 2.C and/or other programming experience 3.Working knowledge of scripting language 4.SystemVerilog experience 5. Matlab experience 6. Experience in FPGA development for RF systems 7. Experience in FPGA development for Software Defined Radio platforms Clearance: Candidate can start with an interim clearance Location: Candidate should expect to be onsite 3 days a week initially with additional flexibility once candidate is up to speed on programs etc. Candidate should live locally at the time of the start date.

Degree Level
Bachelor's Degree	Yes
Design
Digital Circuit Design	10 years
FPGA Hardware Design (Xilinx Vivado)	10 years
Electrical/Electronics
Xilinx FPGA	10 years
Engineering
Experience developing hardware verification plans	10 years
Hardware
Hardware Design	10 years
Programming
VHDL / Verilog	10 years
Signal Processing
ASIC Design	10 years
ASIC verification experience	10 years
Digital Signal Processing	5 years
Software Tools
Vivado Software Experience	10 years
Nice to Have
Degree Level
Masters Degree	Yes
PhD	Yes
Electrical/Electronics
System Verilog UVM	0 years
Networks
Working with Ethernet/Serdes IP	0 years
Programming
MATLAB Programming	0 years
Scripting Languages: Perl, Python, C/C++	0 years
RF/Microwave
Experience in FPGA development for RF systems	0 years
Signal Processing
FPGA development for Software Defined Radio platforms	0 years