Ui Ux Design Jobs 2026 (Now Hiring) – Smart Auto Apply

You are a competitive candidate for this job if you possess these skills and competencies:

. Good communication and documentation skills, with a collaborative and proactive work style.

. Demonstrated ability to work effectively in cross-functional, global teams and contribute to technical reviews.. Strong analytical thinking, hands-on debugging skills, and an eagerness to learn and share expertise within the team.

In this role, you will drive the definition, design, and verification of high-performance analog blocks, IP top level designs and subsystems (floor planning, power delivery, bump maps), collaborating closely with system architects, logic designers, and layout engineers. The ideal candidate is self-driven, detail-oriented, and passionate about analog design in high-speed IO and die-to-die systems. You will facilitate technical discussions, hold design reviews, and play an active role in post-silicon validation and performance optimization. The position also involves providing guidance to layout engineers and mentoring junior analog designers as needed. Strong problem-solving skills, teamwork, and a willingness to share knowledge and collaborate across disciplines are essential. This role offers an opportunity to develop innovative designs and be part of a highly experienced IO and die-to-die design team focused on delivering next-generation high-speed interconnect solutions. This is an on-site role and you are expected to work in the office at least 4 days per week.

Qualifications:

Minimum QualificationsBachelor's degree in Electrical Engineering, Electronics Engineering, or a related field.6+ years of experience in analog/mixed-signal circuit design for high-speed SerDes or similar applications.

Your experience must include:

• Proven experience in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, RX AFE, Transmitter (TX), Power Delivery design, IP floor planning, IP top level performance simulation, signal integrity analysis.
• High-speed IO calibration and training algorithms.
• High-speed communication standards such as UCIE and PCIe (Gen5/Gen6/Gen7).
• Core analog design principles, including noise, linearity, matching, and stability.
• Hands-on experience with advanced FinFET CMOS process technologies.
• Analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent.
• Post-silicon validation, lab measurements, and debug of analog circuits.

Preferred Qualifications

• Master's degree in Electrical Engineering, Electronics Engineering, or a related discipline.
• 7+ years of experience in analog design for high-speed SerDes and/or die-to-die applications.
• In-depth understanding of transmitter and receiver design, CDR loops, and equalization techniques.
• Exposure to next-generation high-speed standards such as PCIe 6.0, 800G Ethernet, or JESD.
• Experience with Verilog-A modeling, MATLAB simulations, and automation scripting (e.g., Python, Tcl).
• Strong understanding of signal integrity concepts, channel modeling, and system-level link analysis.
• Background in standard and advanced package technologies.